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PowerPC A2
The PowerPC A2 is a massively multicore capable and multithreaded 64-bit Power Architecture processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz. Each A2 core is capable of four-way multithreading and have 16 KB+16 KB instruction and data cache per core. All core variants execute instructions in-order.
== Design ==
The A2 core is a processor core designed for customization and embedded use in system on chip-devices. It implements the 64-bit Power ISA v.2.06 Book III-E embedded platform specification with support for the embedded hypervisor features. It is a 4-way simultaneous multithreaded core with 4×32 64-bit general purpose registers (GPR) with full support for both little and big endian byte ordering.
The core has a fine grain branch prediction unit (BPU) with eight 1024-entry branch history tables. It has a 16 KB 8-way set-associative level-1 data cache and a 4-way set-associative 16 KB level-1 data cache. It executes a simple in-order pipeline capable of issuing two instructions per cycle; one to the 6-stage arithmetic logic unit (ALU) and one to the optional auxiliary execution unit (AXU).
It includes a memory management unit but no floating point unit (FPU). Such facilities are handled by the AXU, which has support for any number of standardized or customized macros, such as floating point units, vector units, DSPs, media accelerators and other units with instruction sets and registers not part of the Power ISA. The core has a system interface unit used to connect to other on die cores, with a 256-bit interface for data writes and a 128-bit interface for instruction and data reads at full core speed.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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